Conferences

Enabling Time-Critical Applications over Next-Generation 802.11 Networks (Demo Paper)
Sung Kim, Mohammad Mamunur Rashid, Saurabh Deo, Javier Perez-Ramirez, Mikhail Galeev, Ganesh Venkatesan, Sabyasachi Dey, William Li, Dave A. Cavalcanti
IEEE International Conference on Computer Communications (INFOCOM), 2018
Best Demo Award

MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators
Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, and Visvesh Sathe
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2018
Best Paper Award

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor
Fahim U. Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, and Visvesh Sathe
IEEE Symposium on VLSI Circuits (VLSI), 2018

An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/s, 2.58 PJ/Bit in 65-nm CMOS
Rajesh Pamula, Xun Sun, Sung Kim, Fahim U. Rahman, Baosen Zhang, and Visvesh Sathe
IEEE Symposium on VLSI Circuits (VLSI), 2018

A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage Margin Reduction in a 0.6-1.0V Cortex-M0 Processor
Xun Sun, Sung Kim, Fahim U. Rahman, Rajesh Pamula, Xi Li, Naveen John, and Visvesh Sathe
IEEE International Solid State Circuits Conference (ISSCC), 2018

Exploring Computation-Communication Tradeoffs in Camera Systems
Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, and Visvesh Sathe
IEEE International Symposium on Workload Characterization (IISWC), 2017

Motion-Vector Clustering for Traffic Speed Estimation from UAV Video
Ruimin Ke, Sung Kim, Zhibin Li, and Yinhai Wang
IEEE International Smart Cities Conference (ISC2), 2015

E-Prints

Bandwidth Extension on Raw Audio via Generative Adversarial Networks
Sung Kim, Visvesh Sathe
ArXiv, 2019

Journals

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains
Fahim U. Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh Sathe
IEEE Journal of Solid-State Circuits (JSSC), 2019

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
Xun Sun, Fahim U. Rahman, Rajesh Pamula, Sung Kim, Xi Li, Naveen John, and Visvesh Sathe
IEEE Journal of Solid State Circuits (JSSC), 2019

A 65-nm CMOS 3.2-to-86 Mbps 2.58 pJ/b Highly Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction
Rajesh Pamula, Xun Sun, Sung Kim, Fahim U. Rahman, Baosen Zhang and Visvesh Sathe
IEEE Solid-State Circuits Letters (SSCL), 2019

Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors
Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, and Visvesh Sathe
IEEE Transactions on Circuits and Systems - I (TCAS-I), 2018

Real-Time Bidirectional Traffic Flow Parameter Estimation from Aerial Videos
Ruimin Ke, Zhibin Li, Sung Kim, John Ash, and Yinhai Wang
IEEE Transactions on Intelligent Transportation Systems (ITS), 2016